1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device. More particularly, embodiments of the present invention relate to a layout of a memory cell array of a semiconductor memory device formed using a double patterning technology and a method of forming the same.
2. Description of the Related Art
A conventional memory cell array of a semiconductor memory device may include selection lines, a common source line, selection transistors, memory transistors, a plurality of bit lines intersecting with a plurality of word lines, and active devices below the bit lines. The conventional memory cell array, e.g., the bit lines, may be formed by single patterning in accordance with semiconductor high density integration design rules requiring predetermined critical dimensions (CD), e.g., predetermined tolerances of line widths and spaces therebetween. The conventional single patterning may refer to technology of forming patterns of a semiconductor integrated circuit using a single exposure technology.
However, when a layout of a memory cell array is formed using single patterning, resolution of the memory cell array may be substantially limited. For example, it may be difficult to form patterns having CD values, e.g., a pitch of patterns, below about 50 nm. Further, attempts to use double patterning to form a layout of a memory cell array having a reduced pitch have provided minimized symmetry in the main memory cells, so the bit lines and the active devices below the bit lines exhibited non-uniform electrical properties, e.g., non-uniform unit resistance, non-uniform unit capacitance, and so forth.